Technical Projects
Deep dives into hardware design and verification. Emphasizing clean architecture, comprehensive testbenches, and verifiable correctness.
Progressive implementation of RISC-V processor architectures, scaling from single-cycle and multi-cycle designs to a full 5-stage pipelined processor. Features robust hazard handling across all instruction formats (R, I, S, B, J). Currently architecting branch prediction integration utilizing the gshare algorithm.
A digital design project implementing a real-time Morse Code encoder on an FPGA, utilizing Finite State Machines (FSMs) for sequence generation.
A comprehensive collection of FPGA laboratory exercises and projects, covering foundational digital logic design to complex RTL implementations.
An automated control system architected with an Arduino Uno, interfacing relays, motors, and ultrasonic sensors for real-time water level management. Includes an integrated Bluetooth module for remote telemetry and mobile device connectivity.